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TB62217AFG
TOSHIBA BiCD Process Integrated Circuit Silicon Monolithic
TB62217AFG
PWM drive Stepping Motor Driver / Brush DC Motor Driver Selectable, DC-DC Converter and Reset function IC
The TB62217FG is a dual stepping motor driver driven by PWM chopper micro step, with 3- channel step-down DC-DC converters and an external-IC reset function. To drive a two-phase bipolar-type stepping motor, a 16-bit latch and a 16-bit shift register are built into the IC. The IC is suitable for driving stepping motors with low-torque ripple in a highly efficient manner. In addition, a signal axis can be switched to serve as a PWM driver for two DC motors. By equipping the stepping motor driver with Selectable Mixed Decay Mode for switching the attenuation ratio during chopping, and also equipping it with a DC-DC converter, it is possible for the IC to supply external voltage. With a built-in timer that starts running when the IC is supplied with power, the IC can be used in resetting (initializing) external devices.
Weight: 0.45 g (typ.)
Features
* The following motor combinations can be used.
Stepper (1) (2) (3) (4) (5) (6) Dual motors Single motor Single motor DC Large DC (L) Single motor Single motor Dual motors DC Small DC (S) Dual motors Dual motors Quadruple motors
Note
Hereafter, DC Large will be referred to as DC (L) and DC Small will be referred to as DC (S).
Recommended maximum current Stationary current
The large current standard is achieved by shorting a small current H-Bridge across two ICs. In addition, if the thermal setting is designed to be within the prescribed thermal range, the initial torque current can be used as the normal operating current.
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* * * * *
It is possible to supply external voltage by incorporating three step-down 1.5 V to 5.0 V variable DC-DC converters. A Reset function has been added making it possible to deliver an external reset signal. The DMOS motor driver output of this monolithic BiCD IC is capable of achieving a low ON resistance of Ron = 0.6 ( Tj = 25C, 0.6A: typ.) With two sets of internal 16-bit shift register and latch, the IC can drive stepping motors using a 4-bit micro step. Equipped protection circuits: DC-DC converter over current/increased voltage protection, motor over current protection and total IC over temperature protection. In addition, equipped with Power On Reset circuit for initializing the IC when the power is turned on and off. Package: 64-pin Pb-free QFP package with a heat sink (THQFP64-P-1010-0.50) Motor maximum output pressure: 50 V On-chip Mixed Decay Mode enables specification of four-stage attenuation ratio. Chopping frequency can be set by external oscillator. High-speed chopping is possible at 100 kHz or higher. Note: When using the IC, exercise great care in regard to thermal conditions. This device is easy damaged by high static voltage (ESD). For this reason, please handle with care.
* * * *
Please Insert an SBD (Schottky Barrier Diode : Recommended "TSB CRS04" ) between "ODB" pin and "D-GND" pin , if using C channel.
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* Pin
Layout (4-channel DC Motor Mode , example)
Dch Driver
Cch Driver
Ach Driver
Bch Driver
T-HQFP64-1010-P-0.50
Combinations enclosed in the blue dashed lines are used when in DC (L) mode (A- and B-axis drivers in a pair, and C- and D-axis drivers in a pair).
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Cautions on connection to the IC pins
Note1 Note2 Note3 Note4 Note5 Note6 Connect all NC pins (pins left unused) to the lowest potential level (usually to GND). Connect any unused Vref pins (28pin,29pin) to GND. Unused DATA, CLOCK, and STROBE input pins are pulled down internally, so connect them to GND. Please ensure that noise is not introduced into the external circuit Connect any unused RS pins to VM. Connect the feedback pins (FBA, FBB, and FBC) to GND if the corresponding DC-DC converter is not used. Always connect the TEST pin to the lowest potential level (usually to GND). Note7: TEST pin The TB62217FG has a test mode function for inspection at the factory. The test mode reduces the "initial and normal protection mask time" and "ORT output time" to 1/1024 of the respective ratings so as to make the inspection easier. To maintain normal operation, therefore, be sure to connect pin 32 to a ground so that it will not be used. Conditions to use the test mode
Input level High Low 32 standard operation TEST Mode 100k 32 pin: TEST
Note 8
If the IC is inserted in an incorrect orientation, it will be damaged because a high voltage is applied to low-voltage blocks. To avoid such damage, always confirm the position of pin 1 and the position and dimensions of each lead when installing the IC.
Note 9 Note 10 Note11
The IC has no on-chip over voltage protection circuit. Avoid applying a voltage higher than any rated voltage (such as maximum ratings) to the IC. Solder the heat sink provided on the bottom surface of the IC to a ground-level pattern arranged for heat release so as to ensure stable operation and efficient heat release. Once set up, since the IC is not affected by a logical input from a "Don't care" pin even if a voltage is applied to the pin, as long as the applied voltage is not higher than its rating, no problem (such as a malfunction) will occur.
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Pin Descriptions (initial setup mode)
SLEEP = Low supports a write mode for the initial setup or extended setup mode data. (1) Pin description (SETUP mode, that is, initial setup or extended setup mode) (2) Pin description (dual axis stepping motor mode) (3) Pin description (single axis stepping motor and single axis DC (L) mode) (4) Pin description (single axis stepping motor and dual axis DC (S) mode) (5) Pin description (dual axis DC (S) and single axis DC (L) mode) (6) Pin description (dual axis DC (L) mode) (7) Pin description (quadruple axis DC (S) mode)
Pin Name Assignment Table
+
+
+
+
+
+
+
-
-
-
-
-
-
-
17 18 19 20 21 22 23 30 25 26 27 28 29 30 31
(ODC) (FBC) (ODB) (FBB) CC OSC_D NC NC VDIN1 VDIN2 VM (VREF AB) (VREF CD) (FBA) (ODA)
ODC FBC ODB FBB CC OSC_D NC NC VDIN1 VDIN2 VM VREF AB VREF CD FBA ODA
ODC FBC ODB FBB CC OSC_D NC NC VDIN1 VDIN2 VM VREF AB VREF LCD FBA ODA
ODC FBC ODB FBB CC OSC_D NC NC VDIN1 VDIN2 VM VREF AB VREF SCD FBA ODA
ODC FBC ODB FBB CC OSC_D NC NC VDIN1 VDIN2 VM VREF LAB VREF SCD FBA ODA
ODC FBC ODB FBB CC OSC_D NC NC VDIN1 VDIN2 VM VREF LAB VREF LCD FBA ODA
ODC FBC ODB FBB CC OSC_D NC NC VDIN1 VDIN2 VM VREF SAB VREF SCD FBA ODA
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32 33 34 35 36 37 38
TEST DGND1 MGND (OUT C-) (RS C1) (RS C2) (OUT C+)
TEST DGND1 MGND OUT C- RS C1 RS C2 OUT C+
TEST DGND1 MGND OUT LCD- RS C1 RS C2
TEST DGND1 MGND OUT SC- RS C1 RS C2
TEST DGND1 MGND OUT SC- RS C1 RS C2
TEST DGND1 MGND OUT LCD- RS C1 RS C2
TEST DGND1 MGND OUT SC- RS C1 RS C2
Connect to GND
DOUT LC( MGND NC NC MGND OUT LCD( RSD1 RSD2 OUT LCDMGND C_SELECT ENABLE LCD TH_OUT LOGIC OUT STROBE AB NC LGND LGND NC ORT OSC_M -
OUT SC( MGND NC NC MGND OUT SD( RSD1 RSD2 OUT SDMGND C_SELECT ENABLE SD ENABLE SC TH_OUT LOGIC OUT STROBE AB NC LGND LGND NC ORT OSC_M PHASE SD
OUT SC( MGND NC NC MGND OUT SD+ RSD1 RSD2 OUT SDMGND C_SELECT ENABLE SD ENABLE SC TH_OUT LOGIC OUT -
OUT LCD( MGND NC NC MGND OUT LCD+ RSD1 RSD2 OUT LCDMGND C_SELECT ENABLE LCD TH_OUT LOGIC OUT -
OUT SC( MGND NC NC MGND OUT SD+ RSD1 RSD2 OUT SDMGND C_SELECT ENABLE SD ENABLE SC TH_OUT LOGIC OUT ENABLE SB ENABLE SA NC LGND LGND NC ORT OSC_M PHASE SA AGND (LGND) AGND (LGND)
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
MGND NC NC MGND (OUT D() (RSD1) (RSD2) OUT DMGND C_SELECT TH_OUT LOGIC OUT STROBE AB NC LGND LGND NC ORT OSC_M -
MGND NC NC MGND OUT D( RSD1 RSD2 OUT DMGND C_SELECT STROBE CD TH_OUT LOGIC OUT STROBE AB NC LGND LGND NC ORT OSC_M DATA CD
ENABLE LAB ENABLE LAB NC LGND LGND NC ORT OSC_M PHASE SD NC LGND LGND NC ORT OSC_M -
-: Don't care
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Note:H-bridge combination (connection method) for each type of motor driver
VM RRS
VM RRS RS pin B-phase Load PGND Stepping Motor single motor PGND VM RRS RS pin
Mutually connected outside the IC
RS pin
A-phase
Load
RS pin
Load
PGND DC (L) Single motor
PGND
The white circle indicates an IC pin.
Note1: When driving a DC motor in DC (L) mode, avoid an impedance difference outside the IC.
Note2: If the impedance of wiring to mutually connected output transistors is unbalanced, the current that flows through the transistor also becomes unbalanced and may exceed the maximum rating of the transistor, thus damaging the transistor.
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VM RRS RS pin Note Load PGND DC (S) Single motor The white circle indicates an IC pin.
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1. Overall Block Diagram
OSCD FBA ODA FBB ODB FBC ODC CSELECT CC
DC/DC converter DC/DC cnv A
DC/DC converter DC/DC cnv B
DC/DC converter DC/DC cnv C
DC/DC selector
VM-VDD regulator
VSD unit
POR unit (CC) Extended setup unit Init setup unit 16-bit latch Current control data logic circuit Current control 16-bit latch * * These items are provided only on the A- and B-axis inputs. Logic out Chopping reference circuit Chopping waveform generating circuit OSC_M
SLEEP
DATA selector
DATA CLK STROBE
16-bit shift register
Current setting circuit Vref Torque control 4-bit sine D/A (Angle control)
Waveform shaping circuit
TH_OUT Current feedback circuit RS VM VRS unit RS COMP circuit Output control unit Thermal detect
Outputs unit (H-bridge) RESET unit Select Out X
ISD unit
TSD circuit
ORT
POR circuit (VM)
Protection circuits
High-voltage wiring (VM) Logic DATA Analog DATA IC pin
Stepping motor
DC motor
DC motor
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2-1. Input Equivalent Circuits
(1) Logic Input Pin
21 CC * 64: PHASE SB 63: PHASE SD 62: PHASE SC 61: PHASE SA 54: ENABLE SA 53: ENABLE SB 50: ENABLE SC 49: ENABLE SD 1: SLEEP
*
IN 100 k 150 To the internal logic
56
57 LGND
GND
(2) Vref Input Pin
21 CC
28 : Vref AB 29 : Vref CD
2 To the DA circuit
56
57
GND
(3) DC/DC Feed Back Pin (FBx)
150 30 : FBA 20 : FBB 18 : FBC 1.5 V
57
1.05 V
2.01 V
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2-2. Stepping Motor Logic Unit (with the same functions for both an A-/B-axis pair and a C-/D-axis pair)
Function
This circuit receives step current setting data entered from the DATA pin and transfers it to the subsequent stage. It is enabled when the SLEEP pin is high. (If the SLEEP pin is low, the IC enters the initial setup or extended setup mode.)
Step current setting data logic circuit and setup logic 16-bit shift register STROBE CLK DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Current control 16-bit latch
Sleep = H
Torque x 2 bits
Decay x 2 bits B unit side
Current x 4 bits B unit side
Phase x 1 bit B unit side
Decay x 2 bits A unit side
Current x 4 bits A unit side
Phase x 1 bit A unit side
Current feedback circuit (TRQ setting)
B unit side mixed decay timing
DA circuit
B-phase information
A unit side mixed decay timing
DA circuit
A-phase information
Output control circuit
Output control circuit
Once ORT is released, driving the SLEEP pin high puts the IC in a write mode for stepping motor current control data. Driving the SLEEP pin from high to low and back to high clears any latched motor control data (to all low).
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2-3. Initial Setup Logic Unit (available only for the A- / B-axis pair)
Function
This circuit is used to set up driver functions (initial setup) according to signals entered from the DATA pin. The functions that can be set up include motor re-configuration, digital tBLANK, DC-DC converter ON/OFF setting, and DC motor mode Vref (gain) setting. Note: Do not use the TEST mode. Keep all the corresponding bits and any unused pins at a low level.
Logic circuit and setup logic 16-bit shift register STROBE AB CLK AB DATA AB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Initial setup 16-bit latch
16 L
Sleep = L
Motor select (3 bit)
tBLANK AB (2 bit)
tBLANK CD (2 bit)
DCDC select (3 bit)
DC Vref gain (2 bit)
TEST (3 bit)
No use (1 bit)
Note: The setting entered in initial setup mode is in effect if the DATA signal is low when the STROBE signal is supplied. The initial setup mode data is cleared at POR (power-on reset).
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2-4. Extended Setup Logic Unit (available only for the A- and B-axis pair)
Function
This circuit sets up the monitor functions of the driver IC internal circuits according to a signal entered from the DATA pin.
Extended setup logic 16-bit shift register STROBE AB CLK AB DATA AB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Extended setup 16-bit latch
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 H
Sleep = L
Shut down select (4 bit)
Shut down mask (4 bit)
Reset mask (3 bit)
Pre TSD (2 bit)
Reserved
No use (1 bit)
ISD time (1 bit)
Note: The internal-signal monitoring setting (entered in extended setup mode) is in effect if the DATA signal is high when the STROBE signal is supplied. Data for the extended setup mode is cleared at POR (power-on reset).
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3. Current Feedback Circuit and Current Setting Circuit for Motor Driver
Function
The current setting circuit is used to set the reference voltage of the output current using the step current setting data entered from the serial input pin. The current feedback circuit is used to deliver a signal to the output control circuit when the output current reaches the set current. This is done by comparing the reference voltage delivered from the current setting circuit with the potential difference generated when current flows through the current sense resistor (RRS) connected between RS and VM. The chopping waveform generator, to which a capacitor is connected, generates the OSC M (OSC-CLK) as a chopping frequency reference. If the Osc_M pin becomes open, the open condition detection function works, thus shutting down the IC. If the pin is shorted to GND when the IC starts operating, the detection function also works and the IC does not operate.
Torque 0.1
From the logic unit
Current 0~3
OSC_D
DSC Open Short Detect Unit
Vref
Torque control circuit
Step current selector circuit
4-bit DA circuit
Waveform shaper circuit Chopping reference generator circuit Output stop signal (ALL OFF)
Mixed decay timing circuit
Current setting circuit
RS RRS
VRS circuit 1 (detects voltage difference between RS and VM) Current feedback circuit
RS COMP circuit
NF (set current reached signal)
Output control unit
VM
Note: The RE COMP circuit compares the set current with the output current and generates a signal when the output current reaches the set current.
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COSCM
100% 85% 70% 50%
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Chopping reference waveform generator circuit
OSCM
TB62217AFG
4. Output Control Circuit, Current Feedback Circuit, and Current Setting Circuit for Motor Driver
Step current setting data logic circuit Chopping reference generator circuit Mixed decay timing circuit
Output control circuit Current feedback circuit NT set current reached signal
Phase
Decay mode
Charge start
OSC counter
Mixed decay timing Current setting circuit Output stop signal Output control signal U1 U2 L1 L2
OSC counter (2)
Output driver circuit
Output reset signal
Output circuit VM VM-VCC regulator
ISD circuit POR circuit (VM) CC monitoring circuit TSD circuit VSD circuit Reset signal selector circuit
CC
Th_out
Protection circuits Latched-data clear signal
VSD VMR ISD TSD
: DC-DC output voltage monitor : VM power monitor : Over current protection circuit : Over-temperature protection circuit
Logic
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5. Output Equivalent Circuit for Motor Driver
RSA
RRS A
To VM
Output driver circuit U1 U2 L1 L2
U1 U2 OUT A
From output control circuit
L1
L2
OUT A
Phase A
VM
Output driver circuit U1 U2 L1 L2 U1 U2
RSB
RRS B
From output control circuit
OUT B
OUT B M
L1
L2
Phase B
MGND
The motor output H switch block consists of the upper P-channel DEMOS FET and lower N-channel DEMOS FET. Each output DEMOS FET is connected to an over current sense circuit (ISD detection circuit) in parallel.
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6. DC-DC Converter Circuit
When an open detection circuit is available, Osc_D pin is set to open, the IC shuts down. If the pin is shorted to GND at startup, the IC fails to start operating. (It does not detect in a default.) In the DC-DC converter operating mode, channel B starts operating before channel A or C.
VDIN OSC_D
COSC_D (120 pF)
CR control circuit
Maximum Rating
A ch
DC-DC converter A control circuit
LDA (330 H) ODA FBA VSD
To output
C_DC_A (100 F)
DGND B ch DC-DC converter B control circuit
LDB (330 H) ODB FBB VSD
C ch
DC-DC converter C control circuit
LDC (330 H) ODC FBC VSD
DGND
Please Insert a SBD( Schottky Barrier Diode : Recommended "TSB CRS04) between "ODB" Pin to "D-GND" pin.
RDCC2 RDCC1
C_DC_C (100 F)
RDCB2 RDCB1
C_DC_B (100 F)
SBD
RDCA2 RDCA1
To output
To output
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7. Reset Circuit (ORT)
This circuit has an open-drain output. If the output is pulled up with a resistor to the supply voltage, its level becomes low (internally on) at reset and high (internally Hi-Z) during normal operation (at a non-reset).
DC/DC conv 3.3 V ORT
1 k
8.
DC-DC Converter Select Circuit (C_SELECT)
*: Each internal circuit resistance varies by 30%.
200 k
To internal 5 V supply voltage
CC
150
C_SELECT 200 k is added if the voltage is 2.5 V
9.
Set Temperature Detection Output Pin (TH-OUT)
It is not necessary to connect a pull-up resistor when choosing ANALOG output mode ( terminal :OPEN)
10. Internal Logic Signal Select Output Pin (LOGIC OUT)
Both the TH-OUT and LOGIC OUT circuits have the same open-drain circuit as the ORT circuit. If their output pins are pulled up with a resistor to the supply voltage, their levels become low (internally on) at reset and high (internally Hi-Z) during normal operation (at non-reset).
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16-Bit Serial Input Signals
Three different pieces of data can be entered and set up by combining the CLK, DATA, STROBE and SLEEP pin inputs. (1) Extended setup mode (for setting up protection circuits) (2) Initial setup mode (for setting up motor drive modes) (3) Stepping motor drive mode (normal drive mode)
Setup Mode Specifications (Initial setup and extended setup modes)
SLEEP
STROBE
CLK
DATA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note: The internal-signal monitoring setting (entered in extended setup mode) is in effect if the DATA signal is high when the STROBE signal is supplied. If the DATA signal is low, initial setup is in effect (initial setup mode).
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(1) Extended Setup Mode Function (write enabled only when SLEEP = L and Setup Select = H)
* In the extended setup mode, the protection circuits are set up and a monitor setup (output of a Lo_out pin) of a shutdown signal etc. is performed.
Default Value 0 Selecting a signal at shut-down These 4 bits select what shut-down signal to produce. See the next item for explanations about the 4-bit data combinations.
Data Bit 0 1 2 3 4 5 6 7 8 9
Name SD SELECT 0 SD SELECT 1 SD SELECT 2 SD SELECT 3 Unused DCDC VSD SD MASK Motor ISD SD MASK TSD SD MASK RESET MASK C RESET MASK B
Function
Setting
0 0 0
0 0 0 0 0 0
Shut-down signal mask
0: Normal operation. See the corresponding item below for explanations about the 3-bit data combinations. 0: Normal operation. 1: If the DC-DC converter concerned is shut down: (1) The RESET signal is not generated. (2) All DC-DC converters other than the DC-DC converter of interest operate normally. (3) The DC-DC converter concerned returns to normal when the SLEEP signal changes from low to high. 12 0 0 1 1 11 ( bit) 0: TSD-20C 1: TSD-30C 0: TSD-40C 1: Analog
10
RESET MASK A
Disabling the RESET signal at the shut-down of the corresponding DC-DC converter.
0
11 12 13 14 15
PRE TSD 0 PRE TSD 1 Unused OSCM/D Watch Dog Setting Unused
Generating a low signal at the Th_out pin at a temperature of the TSD temperature - X. Unused Specifying whether to cause OSC_M and OSC_D to run. Unused
0 0 0 0 0
0: OFF (watchdog disabled) 1: ON (watchdog enabled)
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[Shut-down signal output (SD select)]
These 4 bits are used to select what shut-down signal to generate. Alternatively, they are used to indicate vendor or version code. The shut-down select signals are released when the SLEEP signal changes form low to high.
Data Data (3) L L L L L L L L H H H H H H H H Data (2) L L L L H H H H L L L L H H H H Data (1) L L H H L L H L L L H H L L H H Data (0) L H L H L H L H L H L H L H L H Function Bit Generate the shut-down signal when the channel A DC-DC converter is shut down with DC-DC VSD_H or DC-DC VSD_L. Generate the shut-down signal when the channel B DC-DC converter is shut down with DC-DC VSD_H or DC-DC VSD_L. Generate the shut down signal when the channel C DC-DC converter is shut down with DC-DC VSD_H or DC-DC VSD_L. Unused Generate the shut-down signal when the DC-DC converter is shut down with "DC-DC VSD_H". Generate the shut-down signal when the DC-DC converter is shut down with "DC-DC VSD_L". Generate the shut-down signal when the DC-DC converter is shut down with "Motor ISD". Generate the shut-down signal when the DC-DC converter is shut down with "TSD". Revision (0) Deliver bit 0 of the version code. Revision (1) Deliver bit 1 of the version code. Revision (2) Deliver bit 2 of the version code. Vender code: Always deliver "detected" in the TB62217FG. Unused Unused Unused Unused
*: Data (3 to 0) = "0000" to "0111" are used to indicate a signal filtered in the internal dead-zone time circuit.
[Shut-down mask]
These 3 bits are used to disable the shut-down function concerned. (One bit corresponds to one function. When a bit is high, the corresponding function is disabled. Their default value is "LLLL".) Data (7): If this bit is high, "TSD" is disabled. Data (6): If this bit is high, "Motor ISD" is disabled. Data (5): If this bit is high, "DC-DC VSD" is disabled. *: Data (4): Unused.
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[RESET output mask]
These 3 bits are used as a signal to specify whether to produce the RESET when the respective DC-DC converters are shut down. No low signal is produced as the RESET even if Data (X) = H and one DC-DC channel = H. The default value of these bits is "L, L, L". (When a DC-DC converter is shut down, the RESET is driven low, and all DC-DC channels are turned off.) If the DC-DC converter concerned is shut down: (1) No RESET (ORT) is produced. (2) All DC-DC converters other than that concerned operate normally (rather than being shut down) (3) Changing the SLEEP signal from low to high restarts the DC-DC converter. Data (10): DC-DC converter channel A Data (9): DC-DC converter channel B Data (8): DC-DC converter channel C
[PRE TSD]
A low signal is generated at the TH_OUT pin if the current temperature is X degrees lower than the TSD temperature. In analog output mode, a very low voltage proportional to the temperature is generated. (The analog output mode is dedicated for test use; its specification is not guaranteed and therefore it may not be able to be used in usual operation.) Data (12, 11) = 0, 0: TH_OUT is generated (low level) at the TSD temperature - 20C. Data (12, 11) = 0, 1: TH_OUT is generated (low level) at the TSD temperature - 30C. Data (12, 11) = 1, 0: TH_OUT is generated (low level) at the TSD temperature - 30C. Data (12, 11) = 1, 1: Analog output mode.
[Revision and vender]
The revision and vendor codes are specific to an individual version of product. For example: Revision (0, 1, 2) = (L, L, L) and Vendor = (H) for Toshiba #1.0 Revision (0, 1, 2) = (H, L, L) and Vendor = (H) for Toshiba #1.1 Revision (0, 1, 2) = (L, H, L) and Vendor = (H) for Toshiba #1.2 Revision (0, 1, 2) = (H, H, L) and Vendor = (H) for Toshiba #1.3 Revision (0, 1, 2) = (L, L, H) and Vendor = (H) for Toshiba #2.0
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[OSC_M/OSC_D open-state detection circuit]
The OSC_M/OSC_D open-state detection circuit tries to detect when a capacitor comes off the OSC_M or OSC_D for some reason by monitoring to see if the frequency gets out of the rated frequency range. When it detects such an event, it shuts down the IC. The open-state detection circuit is initially off when the power is turned on. (To cause it to run, a serial signal must be supplied to make the corresponding bit high.) The frequency range settings are stated below.
(1) Shut down if the current frequency does not fall in the range: OSC_M frequency/64 > OSC_D frequency > OSC_M frequency/2 (2) Shut down if the current frequency does not fall in the range: OSC_D frequency x 32 > OSC_M frequency > OSC_D frequency x 2 Example 1: If the OSC_M frequency is 800 kHz The IC is shut down when OSC_D frequency > 400 kHz or OSC_D frequency < 12.5 kHz. 2: If the OSC_D frequency is 100 kHz The IC is shut down when OSC_M frequency > 3200 kHz or OSC_M frequency < 200 kHz.
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(2) Initial Setup Mode Select (write enabled only when SLEEP = L and Setup Select = L)
Name Motor Select0 Motor Select1 Motor Select2 TBlank AB 0 TBlank AB 1 TBlank CD 0 TBlank CD 1 Motor pairing setting (See the corresponding pin assignment table.) Function Setting D2 D1 D0 00 0: Stepper x 2 00 1: Stepper x 1 + DCL x 1 01 0: Stepper x 1 + DCS x 2 01 1: DCL x 1 + DCS x 2 10 0: DCL x 2 10 1: DCS x 4 D4 D3 0 0: (1 / fChop) / 8 x 5 0 1: (1 / fChop) / 8 x 2 1 0: (1 / fChop) / 8 x 3 1 1: (1 / fChop) / 8 x 4 D6 D5 0 0: (1 / fChop) / 8 x 5 0 1: (1 / fChop) / 8 x 2 1 0: (1 / fChop) / 8 x 3 1 1: (1 / fChop) / 8 x 4 0: ON 1: OFF 0: ON 1: OFF 0: ON 1: OFF 0: 1/10 1: 1/20 Default Value 0 0 0
Data Bit 0 1 2 3 4 5 6
Channels A and B Noise rejection dead band time setting (See Note below.)
0
0
Channels C and D Noise rejection dead band time setting (See Note below.) DC-DC converter channel A operation DC-DC converter channel B operation DC-DC converter channel C operation Channels A and B Internal Vref attenuation ratio setting for constant current in DC motor mode Channels C and D Internal Vref attenuation ratio setting for constant current in DC motor mode IC internal test mode setting IC internal test mode setting IC internal test mode setting
0
0
7 8 9
DC/DC A SW DC/DC B SW DC/DC C SW
(Note) (Note) (Note)
10
(A- and B-axis) DC motor Vref (gain)
0
11
(C- and D-axis) DC motor Vref (gain) Test Test Test Unused
0: 1/10 1: 1/20 Always keep this bit low. Always keep this bit low. Always keep this bit low. This bit is not in use. Always keep it low.
0
12 13 14 15
0 0 0 0
Note: The initial setting for DATA bits 7, 8, and 9 is determined according to the value of C_SELECT when the VM power is turned on.
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TB62217AFG
tBLANK (noise rejection dead band time)
The TB62217FG incorporates two different dead band times (blanking times) for different motors to be driven so as to prevent malfunction because of switching noise.
(1) Analog tBLANK (for stepping motor mode)
The noise rejection dead band time (analog tBLANK), defined by the motor's AC characteristics, is fixed within the IC. It is used mainly to avoid misjudging Irr (diode recovery time) when a stepping motor is driven with constant current. It is fixed within the IC; it cannot be altered.
(2) Digital tBLANK (for DC motor mode)
Unlike the analog tBLANK, this tBLANK time, specified when the initial setup mode is selected, is generated digitally from an external chopping period. It is used mainly to avoid misjudging the varistor recovery current that occurs when a DC motor is driven by PWM in the DC motor drive mode. If the Motor Select signal selects the stepping motor mode, the digital tBLANK is nullified (0 s), thus enabling only the analog tBLANK time provided within the IC. Because the digital tBLANK is generated in reference to the OSC_M, it can be changed by altering the OSC_M. (Note that altering the OSC_M also changes other items (motor chopping frequency, dead band time at the time of starting).)
Digital tBLANK time
In the initial setup mode, the tBLANK time can be set to 4 different levels for A-B and C-D pairs as follows:
(1) Immediately after the PHASE has changed
If the PHASE changes, the following time is needed for synchronization with an OSC_M edge and internal synchronization. tBLANK time = time need for synchronization between OSC_M and PHASE + set tBLANK time = internal processing time (OSC_M x 1) + synchronization time (below OSC_M x 1) + set time
(2) Charging in constant-current operation (limiter operation)
tBLANK time = set tBLANK time The set tBLANK time is as follows: tBLANK AB (0, 1) & tBLANK CD (0, 1) =: 0 0: OSC_M period x 5 0 1: OSC_M period x 2 1 0: OSC_M period x 3 1 1: OSC_M period x 4 Caution: For #2.0 and after, tBLANK (0, 0) = OSC_M period x 5.
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TB62217AFG
Digital tBLANK Timing in DC Motor Drive Mode
Digital tBLANK Digital tBLANK
Phase
Digital tBLANK
Digital tBLANK
Digital tBLANK
Iout Charge Iout = 0 Charge start timing in constant-current control Phase switching point Phase switching point
The digital tBLANK time begins immediately after the external PHASE signal is switched or at the charge start timing of the constant-current chopper. The digital tBLANK is effective only in the DC motor drive mode. The decay mode for DC motor driving is "Fast Decay".
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(3) Data for Normal Stepping Motor Operation
The TB62217FG signals for normal stepping motor operation can be entered in much the same manner as the drive data of the Toshiba TB62202AF.
Data Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name Torque A0/B0 Torque A1/B1 Decay Mode B0 Decay Mode B1 Current B0 Current B1 Current B2 Current B3 Phase B Decay Mode A0 Decay Mode A1 Current A0 Current A1 Current A2 Current A3 Phase A Channel A current attenuation ratio setting (Mixed Decay Mode) Channel B current attenuation ratio setting (Mixed Decay Mode) Current range setting Function A1/B1 0 0 1 1 B1 0 0 1 1 Setting A0/B0 0: 50% 1: 70% 0: 85% 1 : 100% B0 0 : 12.5% Decay Mode 1 : 37.5% Decay Mode 0 : 75% Decay Mode 1 : Fast Decay Mode(100%)
Channel B current setting 4-bit current data (Using 4 data bits can divide each step into 16.) ("0000": All-output OFF mode) Channel B current phase information
See Setting Table (3).
1: OUT B+ is high. 0: OUT B- is high. A1 0 0 1 1 A0 0 : 12.5% Decay Mode 1 : 37.5% Decay Mode 0 : 75% Decay Mode 1 : Fast Decay Mode(100%)
Channel A current setting 4-bit current data (Using 4 data bits can divide each step into 16.) ("0000": All-output OFF mode) Channel A phase information
See Setting Table (4).
1: OUT A+ is high. 0: OUT A- is high.
SLEEP
STROBE
CLK DATA
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
The initial setup latch, extended setup latch, or normal motor latch is selected as a write latch according to the logical level of the SLEEP signal and the polarity of the DATA signal at an STROBE signal edge. If the SLEEP signal is low, the setup latch is selected when the STROBE changes from low to high (initial setup if DATA = low and extended setup if DATA = high). If the SLEEP is high, the normal motor latch is selected. Don't care the level of the SLEEP during data transfer. The stepping motor latches (for both A-B and C-D pairs) are initialized when the SLEEP signal changes from high to low or from low to high. All registers are initialized at POR. The pins used to write during SLEEP include the DATA AB, CLOCK AB, and STROBE AB pins.
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Setting Table (1) D0 and D1
Torque setting The peak torque current can be switched using 2-bit data. (Switching is the same for both the A-B and C-D pairs.)
Data Bit Name Function Torque 1 0 0 1 Torque0 Torque1 Sets current range 0 1 1 Torque 0 0 1 0 1 Setting Torque (typ.) 50% 70% 85% 100%
Setting Table (2) D2, D3, D9, and D10
Decay mode x1 and x0 settings A value of 37.5% is recommended for a typical condition. Data of (0, 0) specifies a 12.5% decay mode.
Data Bit Name Function Decay Mode 1 0 2 3 9 10 Decay Mode A1/A0 Decay Mode B1/B0 Sets mixed decay 0 1 1 Decay Mode 0 0 1 0 1 Setting Decay mode Mixed Decay Mode: 12.5% Mixed Decay Mode: 37.5% Mixed Decay Mode: 75% Fast Decay Mode (100%)
Setting Table (3) D4, D5, D6, and D7
Current B setting
Data Bit 4 5 6 7 Step 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Current B3 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Current B2 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Current B1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Current B0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Set angle (degrees) 90 84 79 73 68 61 56 51 45 39 34 28 23 17 11 6 0 Current (%) 100 100 98 96 92 88 83 77 71 63 56 47 38 29 20 10 0
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Setting Table (4) D11, D12, D13, and D14
Current A setting
Data Bit 11 12 13 14 Step 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Current A3 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Current A2 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Current A1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Current A0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Set angle value (degrees) 90 84 79 73 68 61 56 51 45 39 34 28 23 17 11 6 0 Current (%) 100 100 98 96 92 88 83 77 71 63 56 47 38 29 20 10 0
Setting Table (5)
D8 and D15
Phase A setting (this table applies also to phase B.) The polarity of the phase A current of a stepping motor is determined as listed below.
Data Bit Name Function Phase 0 Switches phase 1 Setting Phase OUT A: L, OUT A-: H OUT B: L, OUT B-: H OUT A: H, OUT A-: L OUT B: H, OUT B-: L
8 15
Phase B Phase A
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Functions of External Input Pins
(1) PHASE Input Pin (PHASE X)
This pin indicates the polarity of the H switch used in driving a DC motor. PWM can be applied by performing time control (duty control) on this pin.
Pin No. 61 64 62 63 Name PHASE SB SC SD SA Switches phase Function Logical Level L H Setting Phase OUT X: L, OUT X-: H OUT X: H, OUT X-: L
(2) ENABLE Input Pin (ENABLE X)
This pin indicates whether to supply the power to a DC motor to be driven.
Pin No. 54 53 50 49 Name ENABLE SB SC SD SA Function Whether to activate the output Logical Level L H Setting Enable OFF (All transistors for the H switch are off.) Active
(3) SLEEP Input Pin
When the level of this pin is switched from high to low or low to high, all motor drive registers are cleared (all bits of the 16-bit latch for selecting a motor drive are cleared to low). After the IC is shut down in motor ISD operation, changing the SLEEP signal from high to low and to high again causes the IC to return to normal.
Pin No. Name Function Logical Level L H Setting Sleep Power consumption reduction mode and initial setup mode Motor operation mode
1
SLEEP
Power saving mode
(4) C_SELECT Input Pin
This pin determines which DC-DC converter to run (ON-OFF combinations) when the power is turned on.
Pin No. Name Function Logical Level Low DC-DC converter mode at start A ch: OFF B ch: OFF C ch: OFF A ch: ON B ch: ON C ch: OFF A ch: OFF B ch: ON C ch: ON Setting Phase
48
C_SELECT
Mid
High
Note: If the C_SELECT pin is on the mid level, channel B is turned on before channel A. If it is high, channel B is turned on before channel C.
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Protection Operations
(1) When the RESET output mask is "1" in the extended setup mode
Detected Error and Detection Block DC/DC A DC/DC B DC/DC C VSD Not detected Detected Not detected Not detected Not detected Not detected VSD Not detected Not detected Detected Not detected Not detected Not detected VSD Not detected Not detected Not detected Detected Not detected Not detected Motor ISD Not detected Not detected Not detected Not detected Detected Not detected Entire IC TSD DC/DC A Operation State DC/DC B DC/DC C Motor Reset Output Reset Method
Not Normal Normal Normal Normal detected operation operation operation operation Not detected DCDC OFF Normal Normal Normal operation operation operation DCDC OFF Normal Normal operation operation DCDC OFF Normal operation OFF Shut down
H H H H L pulse L
SLEEP/POR SLEEP/POR SLEEP/POR SLEEP/POR POR
Not Normal detected operation
Not Normal Normal detected operation operation
Not Normal Normal Normal detected operation operation operation Detected Shut down Shut down Shut down
Stop state in the protection operations listed above * * * * Shut-down = all the functions stop as a failure related to the entire system occurs. They can be restarted only by initializing using the POR when the VM power is turned on again. OFF = only the motor block stops operating. It can be restarted by changing the SLEEP signal from high to low and to high again. L Pulse: The ORT keeps producing low pulses for 40 ms (if OSCM = 800 kHz). DC-DC OFF = only the DC-DC converter concerned stops operating. It can be restarted as stated below depending on the logic level on which the SLEEP signal is when the converter stops operating. (1) If the SLEEP is low when the DC-DC converter stops, it can be restarted by changing the SLEEP signal from low to high. (2) If the SLEEP is high when the DC-DC converter stops, it can be restarted by changing the SLEEP signal from high to low and to high again.
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(2) When the RESET output mask is "0" in the extended setup mode
Detected Error and Detection Block DC/DC A DC/DC B DC/DC C VSD Not detected Detected Not detected Not detected Not detected Not detected VSD Not detected Not detected Detected Not detected Not detected Not detected VSD Not detected Not detected Not detected Detected Not detected Not detected Motor ISD Not detected Not detected Not detected Not detected Detected Not detected Entire IC TSD Operation State DC/DC A DC/DC B DC/DC C Motor Reset Output Reset Method
Not Normal Normal Normal Normal detected operation operation operation operation Not detected Not detected Not detected Shut Down Shut Down Shut Down Shut Down Shut Down Shut Down Shut Down Shut Down Shut Down Shut Down Shut Down Shut Down OFF Shut Down
H L L L L Pulse L
POR POR POR SLEEP/POR POR
Not Normal Normal Normal detected operation operation operation Detected Shut Down Shut Down Shut Down
Stop state in the protection operations listed above * * * Shut-down = all the functions stop as a failure related to the entire system occurs. They can be restarted only by initializing using the POR when the VM power is turned on again. OFF = only the motor block stops operating. It can be restarted by changing the SLEEP signal from high to low and to high again. Low Pulse: Low pulses are generated for 40 ms (if OSCM = 800 kHz).
Protection Circuit Dead Band Time
(example in which the reference clock (Osc_M) frequency is 800 kHz)
Protection Function TSD Block Detected Entire IC DC-DC converter ISD Motor 4 to 8CLK 5 to 10 s 15 to 20 s Protection Mask Width 12 to 16CLK No function is available Example: Time for OSCM = 800 kHz 15 to 20 s
Reset Method Supplying VM power again
Driving the SLEEP pin low or supplying VM power again Supplying VM power again
VSD
DC-DC converter
12 to 16CLK
Note: To put protection into effect, the protection circuit must keep operating for at least the time stated above.
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(1) Extreme Voltage Drop Protection Function VSD (when detected, the IC is shut down)
Set voltage +40% (typ.) Set voltage DC-DC converter Channel A/B/C output GND Reset output GND 12~16 CLK Set voltage -30% (typ.)
(2) Extreme Voltage Drop Protection Function VSD During Current Limiter Operation (when detected, the IC is shut down)
Set voltage +40% (typ.) Set voltage DC-DC converter Channel A/B/C output GND Current limiter operation GND Reset output GND
-30%
OSC_D: 3 CLK Set voltage -15% (typ.)
Limiter state
(3) IC Overheat Protection Function (TSD) (when detected, the IC is shut down)
Overheat protection value
IC junction temperature 12~16 CLK Reset output GND
Note: A low-pulse period of 40 ms is applied when OSC_DM frequency = 800 kHz and clock = 1.25 s.
4)
Motor Over Current Protection Function (when detected, only the motor is stopped)
Over current Motor output current GND Reset output GND 4~8 CLK 32768 clock (40 ms typ.)
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Power Supply Sequence
If the C_SELECT pin is driven mid or high The 1st DC-DC converter represents channel B, and the 2nd DC-DC converter, channel A or C.
6V
6V
POR
10 s POR
Internal logic start 10 ms 20 ms 1st DC-DC converter operation start 1st DC-DC converter 20 ms 2nd DC-DC converter operation start 2nd DC-DC converter Protection mask end Protection mask 100 ms ORT ORT Serial data acceptable max 320 ms Internal logic
Note: If the C_SELECT pin specifies that all DC-DC converters be off, the ORT reset time is 320 ms. If serial data specifies DC-DC converters be turned on after the power is turned on (C_SELECT: Low)
DC-DC converter channel A operation start
Channel A protection mask 100 ms
DC-DC converter channel B operation start
Channel B protection mask 100 ms
DC-DC converter channel C operation start
Channel C protection mask 100 ms
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Maximum Ratings (Ta = 25C)
Characteristics Motor output voltage Motor output current (Note 1) (Note 2) Symbol VM IOST IOSAP IOSAE ICO A DC-DC converter output current IDC B IDC C Current detection pin voltage Reset pin supply voltage Reset output current Logic input voltage VRS VRST IRST VIN Rating 50 1.3 8? 3 750 400 400 VM 4.5 5
-60 -0.4 to 6.0
Unit V A/phase A A mA mA mA V V mA V W Stepper
Remark
DC motor S (500 ns) DC motor S (100 ms)
1.25 Power dissipation PD 4.2 Operating temperature Storage temperature Junction temperature Topr Tstg Tj
-40 to 85 -55 to 150
When Ta exceeds 25C, this figure must be de-rated by 10.0mW /C. (Note 3) When Ta exceeds 25C, this figure must be de-rated by 33.65mW /C. (Note 4)
W C C C
150
Note 1: See other tables for pairing. Note 2: Peak maximum during DC motor drive (below 500 ns) Note 3: Stand-alone measurement (Ta = 25C) Note 4: When the IC is mounted on a dedicated board (Ta = 25C) Ta: IC ambient temperature Topr: IC ambient temperature during operation Tj: IC chip temperature during operation The maximum Tj value is limited by the TSD (thermal shut-down circuit) temperature
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Recommended Operating Conditions (Ta = 0 to 85C)
Characteristics Symbol Test Condition Excluding motor block Motor block IOLA Stepper Output current IOSL DC Per phase (in single-axis drive) at Ta = 25C Per H-bridge with peak of 500 ns at Ta = 25C Per H-bridge with pulse of 100 ms at Ta = 25C Min 6 (Note 1) 18

Typ. 27 27 0.6 0.8 0.8

Max 40 40 1.0 6.4 2.4 100
Unit V
VM supply voltage
VM
A
DC-DC converter initial output current
IDCi A Before the ORT signal is output (Note 2) IDCi B IDCi C Before the ORT signal is output (Note 2) IDC A After the ORT signal is output After the ORT signal is output
mA
100 600 300 5.0 25

mA mA mA V MHz kHz
DC-DC converter output current Logic input voltage Clock frequency Motor chopping frequency range
IDC B IDC C VIN fCLK fchop
GND 1.0
3.3
100
800
VM = 40 V
Vref reference voltage input range
Vref
0.8
2.0
3.0
V
Note 1: A voltage of 7 V or higher is recommended for typical use. A VM voltage range between 6 V (POR voltage) and 7 V inclusive allows the DC-DC converter to exhibit much the same characteristics as when VM = 7 V (except that the voltage error becomes 10%). However, it is recommended to use the IC at 7 V or higher (partly to allow for a margin of stability), because both the rising POR (power-on reset voltage) and falling POR (shut-down voltage) are 6 V. Note 2: When the power is turned on, soft start is put in effect by limiting the current to the DC-DC converter input block. The limited current results in the output current being limited. If an attempt is made to turn on the power with a load current flowing, it is likely that the DC-DC converter may fail to start or that the output voltage may abruptly increase when the soft-start current is switched.
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Motor Block Electrical Characteristics 1
Characteristics Logic input voltage Logic input clamp voltage Logic input hysteresis Logic input current HIGH LOW Symbol VIH VIL VIK VIN(HIS) IIN(H) IIN(L) IM1 DC DC Test Circuit DC
(unless otherwise specified, Ta = 25C and VM = 18V ~ 40 V)
Test Condition CLK, STROBE, DATA, ENABLE, SLEEP, and PHASE logic input pins IIK = -10 mA CLK, STROBE, DATA, ENABLE, and SLEEP input pins Vin = 3.3 V at each of the CLK, STROBE, DATA, ENABLE, and SLEEP logic input pins Sleep Mode Sleep = L, ALL DC/DC = OFF (IC bias Current) DC IM2 Sleep = H OSC_D = 100 kHz, Motor = OFF DC/DC_A = OFF DC/DC_B = 1.5 V DC/DC_C = 3.3 V Iout_chB + Iout_chC = 10 mA VRS = VM = 40 V, Vout = 0 V, Output OFF Mode DC IOL VRS (HH) VRS (HL) VRS (LH) VRS (LL)
Iout1 Iout2
Min 2.0

Typ.

Max
Unit
0.8
-0.4
V
0.1

0.2

0.3 60 60 2
V
A
Operating current (VM pin)
mA

15
Output standby current Output leakage current
Upper side Lower side
IOH
0
-1

1
A
VRS = VM = Vout = 40 V Output OFF Mode Vref = 2.0 V, Vref (gain) = 1/10, TORQUE = (H.H) = 100%
1
HIGH (reference) Comparator reference voltage ratio MIDDLE HIGH MIDDLE LOW LOW Output current difference between channels in constant-current mode Constant-current output setting difference RS pin current
100 85 70 50

DC
Vref = 2.0 V, Vref (gain) = 1/10, TORQUE = (L.H) = 85% Vref = 2.0 V, Vref (gain) = 1/10, TORQUE = (H.L) = 70% Vref = 2.0 V, Vref (gain) = 1/10, TORQUE = (L.L) = 50%
% 83 68 48
-5 -5
87 72 52
DC
Output current difference between adjacent channels at Iout = 600 mA Iout = 600 mA VRS = 40 V, VM = 40 V Iout = 0.6 A, Tj = 25C, normal direction Iout = 0.6 A, Tj = 25C, reverse direction Iout = 0.6 A, Tj = 105C, normal direction Iout = 0.6 A, Tj = 105C, reverse direction
5
%
DC DC
5 10 0.72 0.72
%
A
IRS RON (D-S) 1 RON (D-S) 1
0.6 0.6 0.78 0.78
On-state resistance between motor output transistor drain and source
DC RON (D-S) 2 RON (D-S) 2
1.01 1.01
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Motor Block Electrical Characteristics 2
Characteristics Vref input voltage Vref input current Symbol Vref Iref Vref (Gain10) Vref (Gain20) VMR (Up) VMR (Down) Cosc_M ISD (Note) Test Circuit DC DC
(unless otherwise specified, Ta = 25C and VM =18V ~ 40 V)
Test Condition When motor output is active When motor output is inactive and Vref = 2.0 V When motor output is active and Vref = 2 V Min 0.8
Typ.

Max 3.0 1.0 1/10.4
Unit V
A
1/9.6 1/19.2
1/10 1/20 14 14 220 5.0
Vref attenuation ratio
DC
1/20.8 15 V
6.0
Motor power return voltage
DC 13
Recommended capacitance for OSC_M pin Operating current for motor over current protection circuit
External capacitance at fosc_M = 800 kHz fchop = 100 kHz
pF A
DC
3.0
Note: Over current protection circuit If an abnormal current higher than the corresponding rating flows through a motor, the overcurrent protection circuit triggers the internal shut-down circuit to turn off the output block. In this case, the currently latched function data is cleared. The overcurrent protection circuit is kept tripped for the motor block until (1) the power is turned on again or (2) the SLEEP returns to a high level. If ISD comes in effect, the output becomes inactive (ALL OFF state) and is kept so until a normal condition is recovered. However, be sure to insert a fuse into the power supply for sake of fail-safe.
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Electrical Characteristics DC_3 (unless otherwise specified, Ta = 25C, VM =18V ~ 40 V, and motor Iout = 1.0 A)
Characteristics Symbol Test Circuit Test Condition
A = 90 (16) A = 84 (15) A = 79 (14) A = 73 (13) A = 68 (12) A = 62 (11) A = 56 (10) A = 51 (9)
Min

Typ. 100 100 98 96 92 88 83 77 71 63 56 47 38 29 20 10 0
Max

Unit
93 91 87 83 78 72 66 58 51 42 33 24 15 5
97 93 88 82 76 68 61 52 43 34 25 15
Chopper current vector
DC
A = 45 (8) A = 40 (7) A = 34 (6) A = 28 (5) A = 23 (4) A = 17 (3) A = 11 (2) A = 6 (1) A = 0 (0)
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Electrical Characteristics DC_4 (unless otherwise specified, Ta = 25C and VM = 40 V)
Characteristics Symbol Test Circuit DC Test Condition (Automatically created within the IC) External capacitance: Under consideration
-20C (serial setting)
Min
Typ.
Max
Unit
Internal logic supply voltage
Vcc
4.5
5.0
5.5
V
TSD operating temperature
TjTSD (Note 1)
DC
130 110 100 90 3.2 0 3.2 0
150
170 150 140 130
C
PRE TSD detection temperature
PRE TSD
DC
-30C (serial setting) -30C (serial setting)
C
Th_out output voltage
VTHO (H) VTHO (L) LO (H) LO (L)
H L H L

V When pull up to 3.3 V with an external resistance of 1 k 0.4
LOGIC OUT
V 0.4
Note: The maximum Tj should not exceed 120C. Thermal shut-down (TSD) circuit TSD comes in effect if the IC junction reaches a rated temperature. It causes the internal reset circuit to operate, thus turning off the output block. (Only one TSD circuit is mounted on the IC.) The TSD operating temperature can be set anywhere in a range between 130C (min) and 170C (max). When TSD comes in effect, the currently latched function data is initialized and the output is stopped. Once the supply voltage drops to or below the POR voltage to shut down the IC, increasing the supply voltage above the POR reset voltage initializes and restarts the IC.
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DC-DC Converter Block Electrical Characteristics (Tj = 0 to 120C and VM = 7 to 40 V)
Characteristics Symbol Test Circuit Test Condition VM = 6.5 V~40 V Tj = 0~120C 0.5 mA~600 mA (large) 0.5 mA~300 mA (small) DCDC output = 1.5 to 5 V VM = 40 V, upper side VM = 40 V, lower side Iout = 300 mA, Tj = 25C, reverse direction Iout = 300 mA, Tj = 105C, reverse direction Iout = 150 mA, Tj = 25C, reverse direction Iout = 150 mA, Tj = 105C, reverse direction Min Typ. Max Unit
Output voltage error
Vout
DC
-7.0
0
7.0
%
DC-DC converter output-off leakage current On-state resistance between output transistor drain and source (large DCDC Unit: Ach)
IOL_DC RON (DS) A1
DC
-0.1 -0.1

0.1 0.1 0.84
A
0.7 0.9 1.4 1.8 1.2 0.6 0.3 0.3
+40 -30 +40 -15
DC RON (DS) A2 RON (DS) BC1 RON (DS) BC2 ILIM (L) DC (large) ILIM (S) DC (small) ILIM (L) DC (large) ILIM (S) DC (small) VSD (U) DC
1.1 1.7
On-state resistance between output transistor drain and source (small DCDC Unit: B, Cch)
DC
2.2 1.6 A 0.85 0.4 A 0.4
+50 -20 +50 -5
0.8
Current limiter value (steady state)
0.5 0.2
Current limiter value (starting)
0.2 In reference to the set voltage. The current limiter is inactive. In reference to the set voltage. The current limiter is active.
+30 -40 +30 -20
Abnormal-voltage protection circuit
VSD (L) VSD (LU) VSD (LL)
%
% pF V
OSC_D capacitor value Feedback voltage
Cosc_D VFB
External capacitor value
47

120 1.5 0 2.5 5.0
DC
DC/DC A, B, Cch All OFF C_SELECT voltage VC_sel DC DC/DC A, Bch ON DC/DC Bch, Cch ON
0.8 3.75
1.25 4.5
V
Reset Block Electrical Characteristics DC (Tj = 0 to 120C and VM = 7 to 40 V)
Characteristics Symbol VMR POR output voltage for VM supply voltage detection
(ALL, Up)
Test Circuit
Test Condition Rising side. All functions change from OFF to ON. Falling side. All functions change from ON to OFF. Reset pin voltage = 0.4 V Pulled up to 3.3 V with an external resistance of 1 k
Min 5.2
Typ.
Max 6.0
Unit
DC VMR (ALL, Down) IRST Vort (H) Vort (L) DC DC
V 5.2 2 3.2 0

6.0

ORT signal output current ORT output pin voltage
mA V
0.4
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Motor Block AC Electrical Characteristics
Characteristics Input clock frequency Symbol fCLK tw (CLK) Minimum clock pulse width twp (CLK) twn (CLK) tSTROBE Minimum STROBE pulse width tSTROBE (H) tSTROBE (L) Data setup time tsuSIN-CLK tsuST-CLK thSIN-CLK thCLK-ST Tr(s) Tf(s) Tr(L) Tf(L) tpLH (STB) tpHL (STB) Output switching time tpLH (OscM) tpHL (OscM) tpLH (ENA) tpHL (ENA) tpLH (PHASE) tpHL (PHASE) Noise rejection analog dead band time Motor chopper reference signal oscillation frequency Frequency range in which motor chopping is supported tBLANK (Analog) fOSC_M fchop (Min) fchop (Typ.) fchop (Max) Motor chopping setting frequency fchop (M) AC Output active (Iout = 0.6 A) with fixed steps Output active (Iout = 0.6 A) M_osc CLK = 800 kHz 40 100 150 kHz AC AC AC AC Vin = 3.3 V AC Vin = 3.3 V AC Vin = 3.3 V Test Circuit AC
(Ta = 25C, VM = 40 A, and motor impedance = 6.8 mH/5.7 )
Test Condition Vin = 3.3 V CLK input pin Min 1.0 40 20 20 40 20 20 10 10 10 10
0.1 0.1 0.1 0.1
Typ.

Max 25

Unit MHz
ns
ns
ns
Data hold time
AC
Vin = 3.3 V 6.8 mH/5.7 load (Small mode) 6.8 mH/5.7 load (Large mode) Step Motor mode 6.8 mH/5.7 load between STROBE () and OUT Step Motor mode 6.8 mH/5.7 load between Osc down edge and OUT DC Motor mode Between ENABLE edge and OUT
ns
0.3 0.3 0.3 0.3 15 10 1.2 2.5
0.5 0.5 0.5 0.5
s
0.3 0.3 0.3 0.3

0.9 0.9 0.9 0.9
DC Motor mode Between PHASE edge and OUT
Iout = 0.6 A C_OSC_M = 220 pF
200 600
300 800
400 1000
ns kHz
100
kHz
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Control signal timing chart
tw(CLK)
CLOCK
50%
50
tsuST-CLK
thCLK-ST
twn(CLK)
twp(CLK)
STROBE
50% tSTROBE(H) tSTROBE(L) thCLK-ST tsuSIN-CLK 50% DATA15 DATA0 DATA1 tSTROBE
DATA
50%
OSCM
tpHL(OSCM) tpHL(STB) fOSC_M
OUT A -
50%
tpLH(OSCM) tpLH(STB) 90%
OUT A +
50% 10% tr tf
PHASE
50% tpHL(PHASE)
OUT A -
50%
tpLH(PHASE)
OUT A +
50%
ENABLE
50% tpLH(ENA)
50% tpHL(ENA)
OUT A +
50%
PHASE
OUT A
t
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DC-DC Converter AC Electrical Characteristics (Tj = 0 to 120C and VM = 40 V)
Characteristics Output transistor switching characteristic (large) Output transistor switching characteristic (small) Output transistor feed-through prevention time DC-DC setting frequency Symbol tr_D(L) tf_D(L) tr_D(S) tf_D(S) tOFF fchop_D (OSC_D) Test Circuit AC Test Condition VM = 40 V, DCDC Ach (Large) Min
100
Typ. 0.1 0.1 0.1 0.1 300 100
Max

Unit
s
AC AC AC
VM = 40 V, DCDC B/Cch (small) VM = 40 V
ns 200 kHz
Protection circuit dead band (MASK) time at startup
tStrart _Mask
AC
The DC-DC converter is turned on independently of others, using serial data. fosc_M = 800 kHz and after the STROBE signal has been accepted At fosc_M = 800 kHz and after VM becomes 6 V or higher but before the first DC-DC converter starts. At fosc_M = 800 kHz and after the first DC-DC converter has started but before the second DC-DC converter starts. fosc_M = 800 kHz At fosc_M = 800 kHz and after VM becomes 6 V or lower but before the ORT becomes low. At fosc_M = 800 kHz and after VM becomes 6 V or lower but before the internal logic starts.
100
ms
Initial startup delay time
tstart1
AC
20
ms
Initial startup delay time 2
tstart2
AC

20

ms
Startup soft mode period LVCO detection dead band time
tsoft tLVCO
AC AC
20 10
ms
s
POR detection dead band time
tPOR
AC
10
ms
VM 90% Pch GATE ODX 10% tr D(L) tr D(S) tf D(L) tf D(S) H L Active Nch GATE DGND OFF Nch G) Pch G)
Active Non- Active Active
Non- Active
STROBE
DC/DC output
tStart_Mask
Non- Active
Mask signal
Active Non- Active
OSCD
fchop_D
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Other Electrical Characteristics AC (Tj = 0 to 120C and VM = 7 to 40 V)
Characteristics Startup reset release time 1 (Protection mask time) Startup reset release time 2 (with no DC-DC converter in use) ORT output low-pulse width when the motor ISD is active Symbol trst1 (Init) trst2 (DCDC OFF) trst(ON) Test Circuit AC Test Condition From VM power-on POR release fosc_M = 800 kHz (114688 clock pulses) From VM power-on POR release fosc_M = 800 kHz (262144 clock pulses) fosc_M = 800 kHz (32768 clock pulses) IRST = 20 mA Pulled up to CC with a resistance of 200 Ccc = 0.1 F fosc_M = 800 kHz After POR release fosc_M = 800 kHz fosc_M = 800 kHz Min
Typ. 140
Max
Unit ms
AC
320

ms
AC
40
ms
ORT signal output delay time
tRST (Delay)
AC
50
ns
Internal initial setup timing SLEEP pulse width SLEEP release delay time
tInit_time tSleep (ON) tSleep (delay)
AC AC AC
10

ms
s s
10
10
tLVCO
VM
POR tPOR
POR
Active tInit_time Non- Active Active Non- Active
1'stDC/DC 2'ndDC/DC ORT
t_start1
t_soft
Active Non- Active Active Non- Active H L
t_start2
t_soft
trst1 / trst2
Active Non-Active Active
ORT
Non-Active tRST Delay) trst ON)
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Calculating the Motor Setting Constant Current
The motor setting current value is determined by RRS and Vref as follows:
Iout (max) = Vref (gain) x Vref (V) x
Torque (Torque = 100, 85, 70, 50% : input serial data RRS ( ) x 100%
)
Assume, for example: Vref (gain) = 1/10: The attenuation ratio is typically 1/10 when Vref = 1/10. Vref =2 (V) Torque =100 (%) Producing Iout = 1.0 A requires RRS = 0.20 (at least 0.2 W). The Vref (gain) is fixed at 1/10 for stepping motors and selectable from 1/10 and 1/20 for DC motors. The error of constant current setting is 5 % when excluding Vref and Rs .
Calculating the Oscillation Frequency (chopping reference frequency) for the Motor and DC-DC Converter Blocks
(1) Calculating the OSC Reference Frequency for the Motor Block (typical)
fosc_M = 61820 x C (pF) ^ -0.8043 (kHz) Hence, the OSC frequency for the motor block is about 810 kHz when Cosc_M = 220 pF. The chopping frequency for stepping motors is about 1/8 the above frequency, that is, 810/8 (= 101) kHz. In addition, only the fast decay mode is available for DC motor drive.
(2) Calculating the OSC Frequency for the DC-DC Converter Block (typical)
f OSCD = 5315.3 x C (pF) ^ -0.8341 (kHz) Hence, the OSC frequency for the DC-DC converter block is about 100 kHz when Cosc_D = 120 pF.
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Power Supply Sequence
(1) If C_SELECT = low
VM POR release VM voltage POR Soft start mode 20 ms Active ALL OFF 10 ms ORT 320 ms L Re-writable All clear Initialize DC/DC control DC/DC all off (C_Sel = L) Rewritten with serial data Active OSC_M Non-active Active OSC_D Non-active Re-writable All cleared Initial value Rewritten with serial data All cleared Full mode Non-active H
0 DC/DC status
Init DATA Extended DATA
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(2) Normal Start (C_SELECT = mid or high)
VM POR release
VM = 15.0 V
VM voltage POR Soft start mode 20ms
0 DC/DC status Active ALL OFF Full mode Non-active 10 ms 10 ms ORT
Init DATA Extended DATA
Re-writable All clear Initial value Initialize Rewritten with serial data All cleared
SLEEP
DC/DC control
Controlled by C SELECT
Controlled with serial data
Re-writable All cleared
DC/DC control start Motor driver control OFF (Data cleared) OFF (Data cleared) Operable (if VM = 15 V or higher) OSC_M
Active Non-active Active
OSC_D Non-active Note: POR release Initialize 10 ms Initialize first DCDC start 10 ms DCDC soft start mode 20 ms
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(3) If VM Voltage Drops at Startup (C_SELECT = mid or high)
VM
VM voltage
POR 10 ms 0 Soft start mode 20 ms Below 10 s Active ALL OFF 10 ms Initialize H Full mode Non-active
DC/DC status
ORT L Init DATA Extended DATA Re-writable All clear Initial value Rewritten with serial data All cleared Controlled by C_SELECT Re-writable Controlled with serial data All cleared Active OSC_M Non-active Active OSC_D Non-active
DC/DC control
All clear
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(4) VM Voltage Drop (normal)
VM VM = 15.0 V
VM voltage POR VM = 0 V DC/DC status Active ALL OFF 10 s ORT Non-active H L Re-writable Init DATA Extended DATA Rewritten with serial data ALL L All cleared Re-writable Rewritten with serial data ALL OFF All cleared Active Non-active Active OSC_M Non-active Active OSC_D Non-active
Full mode
DC/DC control
Motor driver control
Operable (if VM = 15 V or higher)
OFF (Data cleared)
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(5) Supply Voltage Drop (if the VM supply voltage does not cross the POR level)
VM = 15 V
VM voltage POR VM = 0 V
DC/DC status
Full mode
Active Non-active H
ORT
ORT = H L
Init DATA Extended DATA
Re-writable Rewritten with serial data All cleared Re-writable All cleared Active Not operating (if VM = 15 V or lower) Non-active Active
DC/DC control
Rewritten with serial data
Motor driver control
OSC_M Non-active Active OSC_D Non-active
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(6) Supply Voltage Drop (if the VM supply voltage crosses the POR level)
VM = 15 V Shut down (ALL OFF) VM voltage
POR
Initialize DCDC start
VM = 0 V 10 s DC/DC Status Full mode ALL OFF 10 ms ORT L Init DATA Extended DATA Rewritten with serial data Re-writable All cleared Re-writable All cleared Active Non-active Active OSC_M Non-active Active OSC_D Non-active 10 ms H Soft start mode 20 ms Full mode Active Non-active
ALL = L
Initial value
Rewritten with serial data
DC/DC control
Rewritten with serial data
ALL = L
Controlled by C_SELECT
Rewritten with serial data
Motor driver control
Not operating (if VM = 15 V or lower)
OFF (DATA = ALL L)
Not operating (if VM = 15 V or lower)
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Mixed decay Mode Current Waveform and Setting
In constant-current control, the current fluctuation width (current pulsating component) decay mode can be set to any of four points, 0 to 3, using 2-bit serial data. The abbreviation "NF" stands for "negative feedback". It refers to a point where the output current has reached the set current value. The lower the mixed decay timing value, the lower is the current ripple component (current crest value), leading to a lower current decay ability.
fchop
CR pin internal clock waveform DECAY MODE 0 12.5% MIXED DECAY NF
Set current value
CHARGE MODE NF: Set current value reached SLOW MODE MIXED DECAY TIMMING FAST MODE CHARGE MODE
MDT
DECAY MODE 1 37.5% MIXED DECAY
NF
Set current value
MDT CHARGE MODE NF: Set current value reached SLOW MODE MIXED DECAY TIMMING FAST MODE CHARGE MODE
DECAY MODE 2 75% MIXED DECAY
NF
Set current value
MDT CHARGE MODE NF: Set current value reached SLOW MODE MIXED DECAY TIMMING FAST MODE CHARGE MODE
DECAY MODE 3 Set current value FAST DECAY
CHARGE MODE NF: Set current value reached FAST MODE 100% 75% 50% 25% 0
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Relationships Between the OSC_M and Output Drive Timing
OSC-charge delay H OSC-fast delay
fosc _M
L tchop Output voltage A Output voltage A H 50% L H 50% 50%
L Set current
Output current L
Charge
Slow
Fast
OSC_M and Charge Delay
A delay of up to 1.25 ns (when fchop = 100 kHz and fCR = 800 kHz) can occur between the OSC waveform and internal OSC_M CLK, because the rising level of the OSC waveform is used in converting the OSC waveform to the internal M_CLK.
CR-CR CLK delay CR waveform
Internal M_CLK
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VSD Threshold Change Timing During DC-DC Converter Block Current Limiter Operation
When the limiter enters an operating state, the VSD circuit starts operating if this state continues for 3 OSC_D periods.
OSC_D OSC_D_CLK (Internal signal) Case 1 Limiter operating state VSD threshold change (L: -15%) Case 2 Limiter operating state VSD threshold change (L: -15%) Case 3
(1) Normal operation continued
(1)
(2) Normal operation continued
Limiter operating state VSD threshold change (L: -15%) Case 4 Limiter operating state VSD threshold change (L: -15%)
(1)
(2)
(3) Normal operation continued
(1)
(2)
(3)
(4) VSD detected shut-down
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Output-stage Transistor Operation Mode
VM
RRS
VM
RRS
VM
RRS
RS pin U1 ON Note U2 OFF U1 OFF
RS pin U2 Note OFF U1 OFF
RS pin U2 Note ON
Load L1 OFF L2 ON L1 ON
Load L2 ON L1 ON
Load L2 OFF
PGND Change mode
PGND Slow mode
PGND Fast mode
Output-stage Transistor Operation Functions
CLK CHARGE SLOW FAST U1 ON OFF OFF U2 OFF OFF ON L1 OFF ON ON L2 ON ON OFF
Note: The above table summarizes how each transistor behaves when the current flows in the indicated direction. The table below summarizes how each transistor behaves when the current flows in the opposite direction.
CLK CHARGE SLOW FAST
U1 OFF OFF ON
U2 ON OFF OFF
L1 ON ON OFF
L2 OFF ON ON
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PD-Ta (package power dissipation)
This item to be revised once package characteristics are fixed.
Transient thermal resistance of THQFP64 stand-alone and on a PC board (for reference only)
5 Rth (stand-alone) Rth (4-layer board) (for reference only) 4
(W)
Power dissipation PD
3
2
1
0 0
25
50
75
100
125
150
175
Temperature (C)
THQFP64-P-1010-0.50
Note: The board assumed in simulation is Toshiba's ideal board (for reference only).
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Operating Time of The Motor Over Current Protection Circuit
(ISD dead band time and ISD operating time)
fosc_M oscillation (chopping reference waveform)
Output stop (RESET state)
Fosc (OSC_M)
min Dead band time ISD BLANK time max ISD operating time
Time when over current starts flowing through the output stage (over current state start)
Reference diagram: Timing chart showing over current flowing through a motor The over current protection circuit has the dead band time to avoid detecting over current accidentally from current spikes in switching. The dead band time is in synchronization with the frequency of the OSC for setting up the chopping frequency (OSC_M). The time between the instant when over current starts flowing through the output stage and the instant when the output stops is as follows: When dead band time = 4 x fosc_M period Minimum: 4 x fosc_M period Maximum: 8 x fosc_M period (+ synchronization time + 1 fosc_M time) However, the operating time stated above applies when the over current flows ideally. The over current circuit may not work depending on the output control mode and timing. Therefore, a protection fuse needs to be inserted in the VM power supply. (The required rating of the fuse varies depending on the conditions under which the IC is used. Therefore, select a rating that will not cause the maximum power dissipation of the IC to be exceeded and that will not pose any problem.)
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TB62217AFG
Application Circuit Example
M
M
For C_SEL:2.5V 200kohm
from ASIC 3.3V from ASIC
from ASIC from ASIC from ASIC from ASIC from ASIC from ASIC
from ASIC
SBD
M
M
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TB62217AFG
Marking
Vendor Name
TOSHIBA 217AF 26GA11
JAPAN
1PIN Mark
(TOSHIBA)
Product Name TB62~ omitted.
Weekly Code Country of Manufacture
1PIN Lot traceability correspondence G lot code Weekly Manufacture year Wafer / Assembly 1 figure Production factory Toshiba Oita factory traceability code
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Package Dimensions (THQFP64-P-1010-0.50)
Heat sink
Weight: 0.45 g (typ.) Note: The heat sink provided on the bottom surface of the package is 5.5 mm x 5.5 mm (tentative).
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